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256-position two-time programmable i 2 c digital potentiometer ad5170 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 256-position ttp (two-time programmable ) set-an d-forget resistance setting allows second-chance permanent programming unlimited adjustments prior to otp (one-time programming) activation otp overwrite allows dynami c adjustments with user defined preset end-to-end r e s istance: 2. 5 k?, 10 k?, 50 k?, 100 k? compact msop-10 ( 3 mm 4. 9 mm) package fast settling ti me: t s = 5 s typ in power-up full re ad/write of wiper register power-on preset to midscale extra package address decod e pins ad 0 and ad1 single-supply 2.7 v to 5.5 v low temperature coefficient: 35 ppm/c low power, i dd = 6 a maximum wide operatin g temperature: C40c to +12 5 c evaluation board and software are a v ail a ble software repla c es c in factory programming applications applic ati o ns systems calibr ation electronics level setting mechanical trimmers? replacement in new d e signs permanent fac t ory pcb settin g transducer adj u stment of pre ssure, tempera t ure, position, chemical, and optical sensors rf amplifier bi asing automotive e l ectronics adjustment gain control and offset a d just ment general overview the ad5170 is a 256-p o si tion, tw o-t i m e p r og ra mma b l e ( t tp) di g i t a l p o te n t i o me te r 1 tha t em p l o y s f u s e link techn o log y t o e n a b l e t w o o p po rt u n i t i e s a t p e rm a n e n t l y p r o g r a m m i n g th e r e sis t a n ce set t ing. otp is a cos t -ef f ec ti v e al t e r n a t i v e t o eemem for u s e r s w h o do not ne e d to pro g r a m t h e di g i t a l p o te n t i o me te r s e t t in g in m e mo r y m o r e t h a n o n ce. this de vic e p e r f o r m s t h e s a me el e c t r on i c a d j u st me n t f u n c t i on a s me ch a n i c a l p o t e n t iom e t e rs o r va r i a b le r e sist o r s wi th e n hance d r e s o l u tion, s o lid- s t a t e r e l i ab i l i t y , and s u p e r i o r lo w t e m p era t ur e co ef f i cien t pe rf o r m a n c e . func tio n a l block di agram v dd g nd sda scl ad0 ad1 w rdac register address decode serial input register b a fuse links 12 / 8 04104-0-001 fi g u r e 1 . the ad5170 is p r og ra mm ed usin g a 2 - wir e , i 2 c? co m p a t i b le dig i t a l i n ter f ace. u n l i mi te d ad j u st men t s a r e a l lo w e d b e fo r e p e r m a n en t l y (t h e r e a r e ac t u al ly tw o o p p o r t uni t ies) s e t t in g t h e r e sis t a n ce val u e . d u r i n g otp ac t i va t i o n , a p e r m a n e n t b l o w f u s e co mman d f r e e z es t h e w i p e r p o s i t i o n (a nalog o us t o placin g ep o x y o n a m e cha n ica l t r im m e r). u n like tradi t io nal o t p dig i tal p o t e n t iomet e rs, t h e ad5170 has a uniq u e t e m p ora r y o t p o v er wr i t e fe a t ur e t h a t al lo ws fo r ne w a d j u s t m e n t s ev en a f t e r t h e fuse h a s been b l o w n . h o w e v e r , t h e otp s e t t in g is rest o r e d d u r i n g subs e q u e n t p o wer - u p co ndi t i on s. thi s fe a t ur e al lo w s us ers t o t r e a t t h es e dig i t a l p o te n t i o me te rs a s vol a t i l e p o te n t i o me te rs w i t h a pro g r a mmabl e p r es et. f o r a p p l ica t ion s tha t p r og ra m t h e ad5170 a t t h e f a c t o r y , ana l o g d e vices o f fers de vice p r o g r a mmin g s o f t wa r e r u nnin g o n w i n d o w s nt?, 2000, an d xp? o p era t ing sys t em s. this s o f t wa r e ef fe c t iv e l y r e places an y ext e r n al i 2 c co n t r o l l ers, t h us enhan c in g t h e t i me-t o - ma rk e t o f t h e us er s sys t em s. 1 the te rms d i gital p o te ntio m e t e r, vr, a n d rda c are us ed i nte rchange a bl y.
ad5170 rev. a | page 2 of 24 table of contents electrical characteristics 2.5 k? ............................................... 3 electrical characteristics 10 k?, 50 k?, 100 k? versions..... 4 timing characteristics 2.5 k?, 10 k?, 50 k?, 100 k? versions.............................................................................................. 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 typical performance characteristics ............................................. 7 test circuits..................................................................................... 11 theory of operation ...................................................................... 12 one-time programming (otp) .............................................. 12 programming the variable resistor and voltage ................... 12 programming the potentiometer divider ............................... 13 esd protection ........................................................................... 14 terminal voltage operating range ......................................... 14 power-up sequence ................................................................... 14 power supply considerations................................................... 14 layout considerations............................................................... 15 evaluation software/hardware..................................................... 16 software programming ............................................................. 16 i 2 c interface .................................................................................... 18 i 2 c compatible 2-wire serial bus ........................................... 20 pin configuration and function descriptions........................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 11/04data sheet changed from rev. 0 to rev. a changes to electrical characteristics table 1 ............................... 3 changes to electrical characteristics table 2 ............................... 4 changes to one-time programming ......................................... 12 changes to figure 37, figure 38, and figure 39 ........................ 14 changes to power supply considerations................................... 14 changes to figure 40...................................................................... 15 changes to layout considerations .............................................. 15 11/03revision 0: initial version
ad5170 rev. a | page 3 of 24 electrical characteristics 2.5 k ? v dd = 5 v 10% or 3 v 10%, v a = +v dd , v b = 0 v, C40c < t a < +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C2 0.1 +2 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C6 0.75 +6 lsb nominal resistor tolerance 3 ?r ab t a = 25c C20 +55 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristics potentiometer divider mo de (specifications apply to all vrs) differential nonlinearity 4 dnl C1.5 0.1 +1.5 lsb integral nonlinearity 4 inl C2 0.6 +2 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C10 C2.5 0 lsb zero-scale error v wzse code = 0x00 0 2 10 lsb resistor terminals voltage range 5 v a ,v b ,v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 5 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage v dd_otp t a = 25c 5.25 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current i dd_otp v dd_otp = 5.5 v, t a = 25c 100 ma power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 9 bandwidth C3 db bw_2.5k code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k?, r s = 0 3.2 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v.
ad5170 rev. a | page 4 of 24 electrical characteristics 10 k ?, 50 k ?, 100 k ? versions v dd = 5 v 10% or 3 v 10%, v a = v dd ; v b = 0 v, C40c < t a < +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ?r ab t a = 25c C20 +20 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristics potentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1 0.1 +1 lsb integral nonlinearity 4 inl C1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C2.5 C1 0 lsb zero-scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 5 v a ,v b ,v w gnd v dd v capacitance 6 a, b c a, c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage 8 v dd_otp 5.25 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 9 i dd_otp v dd_otp = 5.5 v, t a = 25c 100 ma power dissipation 10 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 11 bandwidth C3 db bw r ab = 10 k?, code = 0x80 600 khz r ab = 50 k?, code = 0x80 100 khz r ab = 100 k?, code = 0x80 40 khz total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 different from operating power supply, po wer supply otp is us ed one time only. 9 different from operating current, supply current fo r otp lasts approximately 400 ms for one time only. 10 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 11 all dynamic characteristics use v dd = 5 v.
ad5170 rev. a | page 5 of 24 timing characteristics 2.5 k ?, 10 k? , 50 k?, 100 k? versions v dd = 5 v 10% or 3 v 10%, v a = v dd ; v b = 0 v, C40c < t a < +125c, unless otherwise noted. table 3. parameter symbol conditions min typ max unit i 2 c interface timing characteristics 1 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time 2 t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 see timing diagrams for lo cations of measured values. 2 the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the scl signal.
ad5170 r e v. a | pa ge 6 o f 2 4 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 4. p a r a m e t e r v a l u e v dd to gnd C0.3 v to +7 v v a , v b , v w to g n d v dd terminal current, axCbx, axCwx, bxCwx 1 pulsed 2 0 m a c o n t i n u o u s 5 m a digital inputs and output vo ltage to gnd 0 v to 7 v operating tem p erature range C40c to +125c maximum junction temperature (t jma x ) 1 5 0 c storage temperature C65c to +150c lead temperature (soldering, 10 sec) 300c t h ermal resista n ce 2 ja : msop-1 0 230c/w 1 maximum terminal current is bound b y the maximum cur r ent handling of the s w itches , maxi m um power d i ss ip ation of the package, and maximum appl ied vol t age acros s any two of the a , b, and w terminal s at a given resi st a n ce. 2 package power di ss ipation = ( t jm ax C t a )/ ja . s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5170 r e v. a | pa ge 7 o f 2 4 typical perf orm ance cha r acte ristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-002 v dd = 5.5v t a = 25c r ab = 10k ? v dd = 2.7v f i gur e 2 . r - inl vs . co de vs . sup p l y v o l t a g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-003 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 3 . r - dnl vs . c o de vs . sup p l y v o lta g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode inl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-004 r ab = 10k ? v dd = 2.7v t a = ? 40c, +25c, +85c, +125c v dd = 5.5v t a = ? 40c, +25c, +85 c, +125c f i gur e 4 . inl vs . code vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-005 v dd = 2.7v; t a = ? 40 c, +25c, +85c, +125c r ab = 10k ? f i gur e 5 . dnl vs . c o de vs . t e m p e r a t ur e ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 p o te ntiome te r mode inl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-006 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 6 . inl vs . code vs . sup p l y v o l t age s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-007 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 7 . dnl vs . c o de vs . sup p l y v o l t a g e s
ad5170 r e v. a | pa ge 8 o f 2 4 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-008 r ab = 10k ? v dd = 2.7v t a = ? 40 c, +25c, +85c, +125c v dd = 5.5v t a = ? 40c, +25c, +85 c, +125c f i gur e 8 . r - inl vs . co de vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-009 v dd = 2.7v, 5.5v; t a = ? 40c, +25 c, +85c, +125c r ab = 10k ? f i gur e 9 . r - dnl vs . c o de vs . t e m p e r a t ur e ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 fse, fu ll- sc a l e er r o r ( l sb ) 1.0 1.5 2.0 temperature ( c) ?40 ? 25 ? 1 0 5 20 35 50 65 80 95 110 125 04104-0-010 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 10. f u ll- s c al e e rror v s . t e m p er a t ur e 0 0.75 1.50 2.25 3.00 3.75 4.50 zs e , ze ro-s cale e rror (ls b ) temperature ( c) ?40 ? 25 ? 1 0 5 20 35 50 65 80 95 110 125 04104-0-011 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 11. zero -s c a le e r r o r v s . t e mpe r a t ur e i dd , s u p p l y curre nt ( a) 0.1 1 10 ? 4 0 ? 7 2 6 5 9 9 2 125 temperature ( c) 04104-0-012 v dd = 5v v dd = 3v f i gure 12. sup p l y current v s . t e mper at ur e ?2 0 0 20 40 60 80 100 120 rheostat mode te mp co (ppm/ c) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-013 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85 c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85c, ? 40c to +125 c f i g u re 13. r h e o s t at m o de t e mpco ?r wb /?t v s . code
ad5170 r e v. a | pa ge 9 o f 2 4 ?30 ?20 ?10 0 10 20 p o te ntiome te r mode te mp co (ppm/ c) 30 40 50 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04104-0-014 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85c, ? 40 c to +125 c f i gure 1 4 . p o tentiom e ter m o de t e m p co ?v wb /? t v s . code ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1m 100k 10m 04104-0-015 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 15. g a in vs. f r equ e nc y vs. c o d e , r ab = 2. 5 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04104-0-016 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 16. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04104-0-017 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 17. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04104-0-018 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1k 100k 1m 10m 04104-0-019 100k ? 60khz 50k ? 120khz 10k ? 570khz 2.5k ? 2.2mhz f i gure 19. C3 db bandwidth at c o d e = 0x80
ad5170 rev. a | page 10 of 24 i dd , s u p p ly curre nt (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) 04104-0-020 t a = 25c v dd = 2.7v v dd = 5.5v f i g u re 20. i dd vs . input v o l t a g e 04104-0-021 scl v w f i gure 2 1 . di g i ta l f eedthro u g h 04104-0-025 v w f i g u re 22. m i ds c a l e gli t ch, cod e 0x 80 t o 0x 7f 04104-0-023 scl v w f i gure 2 3 . la r g e s i gna l s e ttli n g t i m e
ad5170 rev. a | page 11 of 24 test circuits f i gur e 24 t o f i g u r e 29 il l u s t ra t e th e t e s t c i r c ui ts tha t def i ne t h e t e st con d i t io ns us e d i n t h e p r o d uc t sp e c if ic a t i o n t a b l es. 04104-0-026 v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n f i gure 24. t e s t c i rc uit for p o tenti o meter d i v i de r n o nl in ea rit y e r r o r (inl, dnl) 04104-0-027 no connect i w v ms a w b dut f i gure 25. t e s t c i rc uit for r e s i s t or p o s i tion non l i n e a r i t y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) 04104-0-028 v ms2 v ms1 v w a w b dut i w = v dd /r nominal r w = [v ms1 ? v ms2 ]/i w f i gur e 2 6 . t e st c i r c ui t fo r wi p e r resi st a n c e 04104-0-029 ? v ms % dut ( ) a w b v+ ? v dd % ? v ms ? v dd ? v dd v a v ms v+ = v dd 10% psrr (db) = 20 log pss (%/%) = f i gure 27. t e st c i rc uit for p o w e r sup p l y s e nsit ivit y ( p ss, pssr) 04104-0-030 +15v ? 15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 28. t e s t c i rc uit for g a in v s . f r eq uenc y w b v cm i cm a nc gnd nc v dd dut nc = no connect 04104-0-032 f i g u re 29. t e s t c i rc uit f o r co m m o n -m ode l e ak ag e cur r e n t
ad5170 rev. a | page 12 of 24 theory of operation sda scl a w b fuses en dac reg. i 2 c interface comparator one-time program/test control block mux decoder fuse reg. 04103-0-026 f i g u re 30. d e t a iled f u nc t i on al bl ock d i ag r a m the ad5170 is a 256-p o si tion, dig i tal l y co n t r o l l ed va r i a b le r e sis t o r (vr) tha t em p l o y s f u s e link t e c h n o log y t o ac hieve me mor y re te n t i o n of re s i st anc e s e tt i n g . an in t e r n al p o w e r - o n p r es et p l aces t h e wi p e r a t mids c a le d u r i ng p o we r - o n . i f t h e ot p f u nc t i o n h a s b e e n a c t i v a te d , t h e de vice p o w e rs up a t t h e us er - d e f in e d p e r m an e n t s e t t ing. one-time programming (otp) p r io r t o o t p ac ti va t i o n , t h e ad5170 p r es ets t o mids cale d u r i n g i n i t ial po w e r - o n . a f t e r th e wi per i s se t a t th e d e s i r e d pos i ti o n , th e r e s i s t a n ce ca n be pe rm a n en tl y se t b y p r ogra m m i n g th e t b i t hig h alo n g wi t h t h e p r o p er co di n g (s e e t a b l e 7 a nd t a b l e 8) and one t i me v dd _ o tp . n o te t h a t f u s e l i n k te ch nolog y of t h e ad517 x fa mi l y o f d i g i t a l p o t s r e q u i r e s v dd _ o t p betw een 5.25 v a nd 5.5 v to b l o w t h e f u s e s to a c hie v e a g i ve n no n v ol a t i l e se t t i n g . on t h e o t h e r h a n d , v dd ca n be 2.7 v t o 5.5 v d u r i ng op e r a t ion. a s a re su l t , s y ste m s u p p ly t h a t is l o we r t h an 5 . 2 5 v r e q u ir es ext e r n a l s u p p l y fo r o n e-t i m e p r og ra mming. n o t e t h a t t h e us er is al lo we d o n l y o n e a t t e m p t in b l o w in g t h e f u s e s. i f t h e us er fa i l s t o b l o w t h e f u s e s a t t h e f i rs t a t t e m p t , t h e f u s e s st r u c t u r es ma y ha ve change d s u ch t h a t t h e y m a y ne ver b e bl o w n re g a rd l e s s of t h e e n e r g y app l i e d a t su b s e q u e n t e v e n t s . f o r det a i l s, s e e t h e p o w e r s u p ply c o n s idera t ion s s e c t io n. the d e v i ce con t r o l cir c ui t has t w o va li da t i o n b i ts, e1 a nd e0, tha t c a n be r e ad bac k t o ch ec k t h e p r og ra mming s t a t us (s ee t a b l e 7). u s ers sh o u ld al wa ys r e ad ba ck t h e valida ti o n b i t s t o en s u r e t h a t t h e f u s e s a r e p r o p erl y b l o w n. af t e r t h e f u s e s ha v e be e n b l o w n, al l f u s e la t c h e s a r e ena b le d u p o n su bs e q u e n t p o w e r - on; t h er e f o r e , t h e o u t p u t co r r es p o n d s t o t h e s t o r e d s e t t ing. f i gur e 3 0 s h o w s a detailed f u nc tio n al b l o c k dia g ra m. programming the variable resi stor and voltage r h eos t at ope r ation the n o minal r e sis t a n c e o f t h e rd a c b e tw e e n t e r m inal a an d t e r m inal b is a v a i la b l e in 2.5 k?, 10 k?, 50 k?, a nd 100 k?. the n o min a l r e sist a n c e ( r ab ) o f th e vr has 256 co n t ac t p o in ts acces s e d b y the wi p e r t e r m inal , p l us th e b ter m inal co n t ac t. the 8-b i t da t a in t h e rd a c la tc h is deco de d t o s e le c t o n e o f 256 pos s i b l e set t in g s . a w b a w b a w b 04103-0-027 f i g u re 31. r h e o s t at m o de conf ig ur at i o n a s sumin g a 10 k? p a r t is us ed , th e wi p e r s f i rst co nn ec t i o n s t a r ts a t t h e b t e r m inal fo r da t a 0x00. b e ca us e t h er e is a 50 ? wi p e r co n t ac t r e sist a n c e , such a co nn e c t i o n y i el ds a mi ni m u m o f 100 ? (2 5 0 ?) r e sis t a n ce betw een t e r m inal w and t e r m ina l b . t h e s e con d co n n e c t i o n is t h e f i rst t a p p o i n t, w h ich co rr es po n d s t o 1 39 ? ( r wb = r ab / 256 + 2 r w = 39 ? + 2 50 ? ) fo r da t a 0x 01. t h e t h ir d conne c t io n is t h e n e x t t a p p o i n t, r e p r e - s e n t in g 178 ? (2 39 ? + 2 50 ?) f o r da t a 0 x 02, a n d s o o n . e a c h l s b da ta val u e in cr ea s e m o v e s th e w i p e r u p th e r e si s t o r la d d e r un ti l th e l a s t ta p po i n t i s r e a c h e d a t 10, 100 ? (r ab + 2 r w ).
ad5170 rev. a | page 13 of 24 d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b sd bit 04104-0-034 f i gur e 3 2 . ad51 70 e q ui v a le nt rd a c cir c ui t the g e n e ral e q u a t i o n t h a t det e r m i n es t h e dig i t a l l y p r ogra mm e d o u t p ut r e sist a n c e b e tw e e n t e r m ina l w an d t e r m ina l b is w ab wb r r d d r + = 2 128 ) ( (1) w h er e d is t h e de cima l e q ui v a l e n t o f t h e b i na r y co de lo ade d i n t h e 8 - b i t r d a c r e g i s t er , r ab is t h e e nd- to -e n d resist a n c e , an d r w is th e wi p e r r e sis t a n ce con t r i b u t e d b y the o n r e sis t an ce o f th e i n t e rn al sw i t c h . i n su mma r y , if r ab = 10 k? a nd t h e a t e r m in a l is o p en- c i rc u i te d, t h e o u tput re s i st an c e r wb is s e t fo r t h e rd a c la t c h co des, as sho w n in t a b l e 5. ta ble 5. co des a nd corr es po n d i n g r wb resist an ce d dec. r wb ? utput state 255 9,961 full scale (r ab C 1 lsb + r w ) 1 2 8 5 , 0 6 0 m i d s c a l e 1 1 3 9 1 l s b 0 100 zero scale (wiper contact resistance) n o t e th a t i n th e z e r o - s ca l e c o n d i t i o n , a fi n i t e w i pe r r e s i s t a n ce o f 100 ? is p r es en t. ca r e sh o u ld b e tak e n t o limi t t h e c u r r en t f l o w b e tw een t e r m i n al w a n d t e r m in al b in t h i s st a t e t o a m a x i m u m p u ls e c u r r en t o f n o m o r e tha n 2 0 ma. o t h e r w is e , deg r ada t io n o r p o ssi b le de st r u c t io n o f t h e i n ter n a l s w i t ch c o n t ac t ca n o c c u r . simi la r to t h e me cha n ic a l p o te n t io meter , t h e r e s i st an ce o f t h e rd a c bet w een th e wi per , t e rmi n al w , a n d t e rm i n al a also p r od u c e s a d i g i tall y c o n t r o ll ed c o m p l e m e n t a r y r e s i s t a n ce , r wa . w h en t h es e ter m inals a r e us e d , t h e b t e r m inal ca n b e op e n e d . s e t t in g t h e r e sis t a n c e val u e fo r r wa st a r ts a t a max i m u m v a l u e o f r e sist a n ce and de cr e a s e s as t h e d a t a lo ad e d i n t h e l a tch in cr e a s e s i n va lue . t h e ge n e ra l e q ua t i o n fo r t h i s o p era t ion is w ab wa r r d d r + = 2 128 C 256 ) ( ( 2 ) fo r r ab = 10 k? a nd t h e b t e r m inal o p en-cir c u i t ed , t h e fol l o w ing o u t p ut r e sist anc e , r wa , is s e t fo r t h e r d a c l a t c h co des, as sho w n in t a b l e 6. ta ble 6. co des a nd corr es po n d i n g r wa resist an ce d dec. r wa ? utput state 2 5 5 1 3 9 f u l l s c a l e 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 , 9 6 1 1 l s b 0 1 0 , 0 6 0 z e r o s c a l e t y p i ca l d e vice -to - de vic e ma tchi n g is p r o c ess lo t dep e nden t an d ma y va r y b y u p t o 30%. s i n c e t h e r e sis t an c e e l em en t is p r o - ces s ed usin g th in f i lm t e chn o log y , th e ch a n g e in r ab wi t h t e m p era t ur e has a v e r y lo w 35 p p m / c t e m p er a t ur e co ef f i cien t. programm ing t h e po tent iomet e r divi der voltage o u tp ut ope r ation t h e digi t a l p o t e n t io m e ter easil y g e n e ra t e s a v o l t a g e di vid e r a t w i p e r - to - b a n d w i p e r - to - a prop or t i ona l to t h e i n put volt age a t a - t o -b . u n lik e t h e p o la r i ty o f v dd to g n d , w h i c h m u st b e p o s i t i ve, vol t age ac ro ss a C b , w C a , and w C b c a n b e a t e i t h e r po l a ri t y . a v i w b v o 04104-0-035 f i gure 33. p o tentiometer m o de c o nf ig ur ation i f ig n o r i n g t h e e f fe c t o f t h e w i p e r r e sist a n ce fo r a p p r o x im a t io n, c o nne c t i ng t h e a te r m i n a l to 5 v and t h e b te r m i n a l to g r ou nd p r o d uces a n o u t p u t v o l t a g e a t t h e w i p e r - t o -b st ar t i n g a t 0 v u p t o 1 ls b les s than 5 v . e a ch ls b o f v o l t a g e is eq ual t o t h e v o l t a g e a p p l ied acr o s s t e r m inal ab divided b y t h e 256 p o si t i o n s o f t h e p o ten t iom e ter divi der . t h e ge n e r a l e q u a t i o n def i n i n g t h e output vo lt age at v w w i t h r e sp e c t to g r o u nd fo r a n y va l i d i n p u t v o l t a g e a p plie d t o t e r m ina l a and t e r m in a l b i s b a w v d v d d v 256 256 256 ) ( ? + = ( 3 ) f o r a m o r e a c cura t e cal c ul a t i o n , wh i c h in c l u d e s th e e f f e ct o f wi p e r r e sist an ce, v w ca n b e fo u nd as b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = (4) ope r a t i o n o f th e d i g i tal po t e n t io m e t e r i n th e di v i de r m o d e re su lt s i n a more a c c u r a t e op e r at i o n o v e r te m p e r a t u r e. u n l i ke t h e rh e o st a t mo de , t h e o u t p ut vol t a g e is dep e n d en t mainl y o n th e ra ti o o f th e in t e rn al r e si s t o r s, r wa and r wb , and n o t t h e ab- s o l u t e v a l u es. th us, t h e t e m p er a t ur e dr if t r e d u ces t o 15 p p m / c.
ad5170 rev. a | page 14 of 24 esd protection al l d i g i t a l i n p u t s s d a , s c l, a d 0, a nd a d 1 a r e p r o t e c te d wi th a ser i es in p u t r e sis t o r a n d p a ralle l z e n e r e s d s t r u ct ur es, as sho w n i n f i gur e 34 a nd f i gur e 3 5 . logic 340 ? gnd 04104-0-037 f i g u re 34. e s d pr ot ec t i o n of d i g i t a l p i ns a, b, w gnd 04104-0-038 f i g u re 35. e s d pr ot ec t i o n of r e s i s t o r t e r m in als terminal voltage operating ra nge the ad5170 v dd to gnd p o wer su p p ly def i n e s t h e b o u nda r y c o ndi t i ons for prop e r 3 - te r m i n a l di g i t a l p o te n t i o me te r op e r a - ti o n . s u p p l y si g n als p r esen t o n t e rm i n al a , t e r m i n al b , a n d t e rm i n al w tha t e x ceed v dd o r gnd wil l be clam p e d b y the i n t e rnal f o r w a r d - b i ased d i o d es (see f i gur e 36). gnd a w b v dd 04104-0-039 f i g u re 36. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and g nd power-up sequence b e ca us e t h e esd p r o t e c t i o n di o d es limi t t h e vol t a g e co m p l i ance a t te r m i n a l a , te r m i n a l b , a n d te r m i n a l w ( s e e f i g u r e 3 6 ) , i t i s i m po r t a n t t o po w e r v dd /gn d bef o r e a p p l yin g a n y v o l t a g e t o t e r m ina l a, t e r m ina l b , an d t e r m ina l w . o t h e r w is e , t h e dio d e wil l be f o r w a r d b i as e d s u c h tha t v dd is p o w e r e d unin t e n t io na l l y a nd ma y a f fe c t t h e r e s t o f t h e us er s cir c ui t . th e ide a l p o w e r - u p s e q u en ce is g n d , v dd , th e di gi tal in p u t s , a n d t h en v a /v b /v w . t h e re l a t i v e ord e r of p o we r i ng v a , v b , v w , a n d th e d i g i tal in p u ts is n o t i m p o r t a n t as lo n g as t h e y a r e p o wer e d a f t e r v dd /gnd . power supply considerations t o m i n i m i z e th e pa c k a g e p i n co u n t , b o th th e o n e - t i m e p r o - g r a mmin g and n o r m al o p er a t i n g v o l t a g e s u p p l i es s h a r e t h e sa m e v dd t e r m inal o f th e ad51 70. the ad517 0 em p l o y s f u s e link t e c h n o log y tha t r e q u ir es 5.25 v t o 5.5 v f o r b l o w in g t h e i n te r n a l f u s e s to a c h i e v e a g i ve n s e t t i n g , but nor m a l v dd ca n be a n y w h e r e betw e e n 2.7 v and 5.5 v a f t e r the f u s e p r og ra mmin g p r o c es s. a s a r e s u l t , d u al v o l t a g e s u p p lies and i s ola t ion a r e n e e d ed i f s y s t em v dd is lo w e r t h a n t h e r e q u ir e d v dd _ o t p . th e f u se p r ogra mmin g s u p p l y (ei t h e r a n o n -bo a r d r e gula t o r o r rac k -m o u n t p o w e r s u p p l y ) m u s t b e ra t e d a t 5. 25 v t o 5.5 v and a b le t o p r o v ide a 100 ma c u r r en t f o r 400 m s f o r s u cces sf u l o n e- t i m e p r o g ra mmin g . o n ce f u s e p r o g ra mmin g is co m p lete d , t h e v dd _ o tp su p p ly m u st b e re mo ve d to a l l o w nor m a l op e r a t ion a t 2.7 v t o 5.5 v and t h e de vice wil l co n s u m e c u r r en t in a ra n g e . fi g u r e 3 7 s h ow s t h e s i m p l e s t i m p l e m e n t a t i o n o f a d u a l s u pp l y r e q u ir emen t b y usin g a j u m p er . this a p p r o a ch s a v e s on e v o l t a g e su p p ly , b u t dr a w s ad di t i o n a l c u r r en t a nd r e q u ir es ma n u a l co nf igura t io n. v dd 5.5v r1 50k ? r2 c1 10 f c2 1nf 250k ? connect j1 here for otp connect j1 here after otp ad5170 04104-0-049 f i g u re 37. p o wer s u p p ly r e qu ire m ent an al t e r n a t e a p p r o a c h in 3.5 v t o 5.25 v sys t em s adds a sig n a l dio d e b e twe e n t h e s y ste m sup p ly and t h e o t p s u p p ly for is ola t ion, as sh o w n i n f i gur e 38 . v dd 3.5v ?5.25v 5.5v d1 c1 1 f c2 1nf apply for otp only ad5170 04104-0-050 f i g u re 38. is ol at e 5. 5 v o t p s u p p ly f r o m 3.5 v to 5. 2 5 v n o r m a l o p e r at ing sup p ly . th e v dd_o t p m u st be remo v e d onc e o t p is comp leted . v dd 2 .7v 5.5v p1 p1=p2=fdv302p, nds0610 r1 10k ? p2 c1 10 f c2 1nf apply for otp only ad5170 04104-0-051 f i g u re 39. is ol at e 5. 5 v o t p s u p p ly f r o m 2.7 v n o r m a l o p er at ing su p p ly . the v dd_o t p s u p p ly m u s t be rem o ved o n c e o t p is comp le t e d . f o r us ers w h o o p era t e t h eir sys t em s a t 2.7 v , us e o f t h e b i d i r e c t io na l lo w t h r e sh old p - c h mos f et s is r e co mm e nde d for t h e su p p ly s is ol a t ion. a s s h o w n i n f i g u re 3 9 , t h is assu me s
ad5170 rev. a | page 15 of 24 t h e 2.7 v sy ste m vol t a g e is a p plie d f i rst, and t h e p1 a nd p2 ga tes a r e p u l l e d to g r o u nd , t h us t u r n in g o n p1 and subs e q u e n t ly p2. a s a re su lt, v dd o f th e ad5170 a p p r o a c h es 2.7 v . w h en t h e ad5170 s e t t in g is f o un d , t h e fac t o r y t e s t er a p p l ies the v dd _ o t p t o b o th th e v dd a nd t h e mos f et s ga tes t u r n i n g o f f p1 a n d p2. the otp co mma nd is exec u t e d a t t h is time t o p r og ra m th e ad5170 while t h e 2.7 v s o ur ce is p r o t ec t e d . o n ce t h e f u s e pro g r a m m i ng i s c o m p l e te d, t h e te ste r w i t h d r a w s t h e v dd _ o t p a nd t h e s e t t in g fo r ad5170 is p e r m a n en tl y f i xed . ad5170 ac hieves th e o t p f u n c tio n thr o ug h b l o w in g in t e r n al f u s e s. u s ers sh ou ld al wa ys a p p l y th e 5.25 v t o 5.5 v o n e-time p r og ra m v o l t a g e r e q u ir e m en t a t t h e f i rs t f u s e pr og ra mmin g a tte m p t . f a i l u r e to c o m p ly w i t h t h i s re qu i r e m e n t ma y l e a d to a cha n g e i n t h e f u s e s t r u c t ur es, r e n d er in g p r og ra mming in op era b le. p o o r pc b la y o u t i n tr o d uce s pa ra si ti cs tha t ma y a f f e ct th e fuse p r o g ra mmin g . ther efo r e, i t is r e co mme n d e d to add a 10 f ta n t al u m c a pa ci t o r i n pa r a ll e l wi th a 1 nf ceramic ca p a c i t o r as c l os e as p o s s i b l e t o th e v dd p i n. the ty p e an d va l u e ch o s e n fo r b o t h c a p a ci t o rs a r e im p o r t an t. this com b ina t i o n o f ca p a ci t o r v a l u e s p r o v ide s b o t h a f a st re sp ons e and l a rge r su p p ly c u r r e n t ha nd lin g w i t h mini m u m sup p ly dr o o p d u r i n g t r a n sien ts . a s a r e s u l t , t h es e ca p a ci t o rs i n cr e a s e t h e o t p p r og ra mming s u cces s b y n o t i n hi b i t i ng t h e p r op er energ y n e e d e d t o b l o w t h e in t e r n al fu se s . a d di ti o n all y , c 1 minimizes tra n sie n t dist urban c e and lo w f r e q u e nc y r i ppl e w h i l e c 2 re d u c e s h i g h f r e q u e nc y noi s e d u r i n g nor m a l op e r a t i o n . layout co nsidera t io ns i t is g o o d p r ac tice t o em p l o y com p ac t, minim u m lead len g t h la yo u t des i g n . th e le ads t o t h e in p u ts sh o u ld be as dir e c t as p o ss ibl e w i t h a m i n i m u m c o ndu c t or l e ng t h . gr ou n d p a t h s shou l d ha v e l o w re s i st anc e and l o w i n d u c t anc e . n o te t h a t t h e d i g i t a l g r ou nd sh ou l d a l s o b e j o i n e d re motely to t h e analog g r o u nd a t on e p o in t t o minimi ze t h e g r o u n d b o u n ce. v dd gnd v dd c1 10 f c2 1nf ad5170 + 04104-0-040 f i g u r e 4 0 . p o w e r su pp l y by pa s s i n g
ad5170 rev. a | page 16 of 24 evaluation software/hardware f i gure 41. a d 5 1 7 0 comp uter s o f t w a re inter f ace ther e a r e tw o wa ys o f co n t r o l l in g th e ad5170. u s ers can ei t h er p r og ra m t h e de vices w i t h co m p u t er s o f t wa r e o r ext e r n al i 2 c co n t r o l l ers. software programming d u e t o t h e advan t a g es o f t h e one-t i m e p r og ra mma b le fe a t ur e , us ers ma y co n s i d er p r og ra mmin g t h e de vice in t h e f a c t o r y b e f o re s h ippi n g t h e f i n a l pro d u c t to e n d - u s e r s . a d i of f e r s de vice p r o g r a m m in g s o f t wa r e t h a t can b e i m pl em e n te d i n t h e f a c t or y on p c s r u n n i ng w i nd ow s ? 9 5 or l a te r . a s a re su lt , ext e r n a l co n t r o l l ers a r e n o t r e quir e d , w h ich sig n if ican t l y r e d u ces de velo p m e n t t i me. t h e p r o g ra m is a n exe c u t a b le f i le t h a t do es n o t r e q u ir e k n o w le dge o f a n y p r og ra mming la n g u a g e s o r p r ogra mming s k il ls. i t is eas y t o s e t u p an d to us e . f i gur e 41 s h o w s t h e s o f t w a r e in t e r f ace . th e s o f t wa r e ca n b e do wnlo ade d fr o m www . a n a lo g . c o m . the ad5170 s t a r ts a t mids cale a f t e r p o w e r - u p p r io r t o o t p p r ogra m m i n g . t o i n cr em en t o r d e cr e m en t t h e r e s i s t a n ce , t h e us er ma y sim p ly m o v e t h e s c r o l l b a rs o n t h e lef t . t o wr i t e an y s p e c if ic va l u e , t h e us er sh o u l d us e t h e b i t p a t t e r n in t h e u p p e r s c r e en an d p r ess t h e r u n b u t t on. th e fo r m a t of wr i t i n g da t a t o t h e de vi ce is sho w n i n t a b l e 7. on ce t h e desir e d s e t t i n g is fo un d , t h e us er p r es s e s t h e p r og ra m p e r m an en t b u t t o n t o b l o w th e i n t e rn al fus e li nk s. t o r e a d th e v a l i d a t i o n b i t s a n d d a t a fr o m th e d e v i c e , th e u s e r sim p l y p r es s e s t h e re ad b u t t o n. the fo r m a t o f t h e r e ad b i ts is shown i n t a bl e 8 . t o a p pl y t h e de vice p r og ra mmi n g s o f t wa r e i n t h e f a c t o r y , us ers m u st m o dif y a p a r a l l el p o r t cab l e a nd co nf igu r e pin 2, pin 3, pin 15, an d pi n 25 fo r s d a_wr i t e, scl, sd a _ r e ad , and d g nd , r e s p e c ti ve l y , fo r th e co n t r o l sig n als (f igur e 42). u s ers sh o u ld als o la y o u t t h e pcb o f the ad5 170 wi th scl and s d a p a ds, as s h o w n in f i gur e 43, s u c h tha t p o g o p i n s ca n be in s e r t e d f o r fac t o r y p r o g ra mming.
ad5170 rev. a | page 17 of 24 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scl r3 100 ? r2 100 ? r1 100 ? sda read write 04104-0-042 f i g u re 42. p a r a l l e l p o r t con n ec t i on. p i n 2 = sda _ w r it e , p i n 3 = scl, p i n 15 = s d a _ r e ad , and pin 2 5 = dgn d . ad5170 b a ad0 gnd vdd w nc ad1 sda scl 04104-0-043 f i g u re 43. r e c o m m e nded a d 51 7 0 pc b lay o ut. the scl and sd a pads allo w pogo p i ns to b e i n ser t ed so that sig n a l s c a n b e co m m un ic ated th rou g h th e pa r a ll el p o r t f o r pr o g r a mm ing (f i g ur e 42 ).
ad5170 rev. a | page 18 of 24 i 2 c interface table 7. write mode s 0 1 0 1 1 ad1 ad0 w a 2t sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 8. read mode s 0 1 0 1 1 ad1 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte s = start condition. p = stop condition. a = acknowledge. ad0, ad1 = package pin programmable address bits. x = dont care. w = write. r = read. 2t = second fuse link array for two-time programming. logic 0 corresponds to first trim. logic 1 corresponds to second trim. note that blowing trim #2 before trim #1 effectively disables trim #1 and in turn only allows one-time programming. sd = shutdown connects wiper to b terminal and open circuits the a terminal. it does not change the contents of the wiper register. t = otp programming bit. logic 1 permanently programs the wiper. ow = overwrite the fuse setting and program the digital potentiometer to a different setting. note that upon power-up, the digital potentiometer presets to either midscale or fuse setting depending on whether the fuse link has been blown. d7, d6, d5, d4, d3, d2, d1, d0 = data bits. e1, e0 = otp validation bits. 0, 0 = ready to program. 1, 0 = fatal error. some fuses not blown. do not retry. discard this unit. 1, 1 = programmed successfully. no further adjustments are possible.
ad5170 rev. a | page 19 of 24 04104-0-044 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p f i g u re 44. i 2 c inter f a c e d e ta il ed ti mi ng di a g r a m 04104-0-045 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5170 r/w a0 sd 0 o w x x x 1 9 d7 d6 d5 d4 d3 ack by ad5170 frame 3 data byte 1 9 t stop by master 9 d2 d1 d0 ack by ad5170 f i g u re 45. w r it ing t o t h e r d a c r e g i s t e r 04104-0-046 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5170 r/w d7 d6 d4 d3 d2 d1 d0 1 9 e1 e0 x x x ack by master frame 3 data byte 1 9 d5 stop by master 9 xx x no ack by master f i gur e 4 6 . re a d i n g da t a fr om the rd a c re gi st e r
ad5170 rev. a | page 20 of 24 i 2 c compatible 2-wire serial bus the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 45). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit deter- mines whether data is read from, or written to, the slave device). ad0 and ad1 are configurable address bits which allow up to four devices on one bus (see table 7). the slave address corresponding to the transmitted address bits responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. if the r/ w bit is high, the master will read from the slave device. if the r/ w bit is low, the master will write to the slave device. 2. in the write mode, the second byte is the instruction byte. the first bit (msb), 2t, of the instruction byte is the second trim enable bit. a logic low selects the first array of fuses, and a logic high selects the second array. this means that after blowing the fuses with trim#1, the user still has another chance to blow them again with trim#2. note that using trim#2 before trim#1 effectively disables trim#1 and, in turn, only allows one-time programming. the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. also, during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the third msb, t, is the otp (one-time programmable) programming bit. a logic high blows the poly fuses and programs the resistor setting permanently. for example, if the user wanted to blow the first array of fuses, the instruction byte would be 00100xxx. to blow the second array of fuses, the instruction byte would be 10100xxx. a logic low of the t bit simply allows the device to act as a typical volatile digital potentiometer. the fourth msb must always be at logic 0. the fifth msb, ow, is an overwrite bit. when raised to a logic high, ow allows the rdac setting to be changed even after the internal fuses have been blown. however, once ow is returned to a logic zero, the position of the rdac returns to the setting prior to overwrite. because ow is not static, if the device is powered off and on, the rdac presets to midscale or to the setting at which the fuses were blown, depending on whether the fuses have been permanently set. the remainder of the bits in the instruction byte are dont care bits (see figure 45). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 44). 3. in the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from the write mode, with eight data bits followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 46). following the data byte, the validation byte contains two validation bits, e0 and e1. these bits signify the status of the one-time programming (see figure 46). 4. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 45). in read mode, the master issues a no acknowledge for the 9 th clock pulse (i.e., the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 46). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output updates on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5170 rev. a | page 21 of 24 table 9. valida tion status e 1 e 0 s t a t u s 0 0 ready for progr a mming. 1 0 fatal error. som e fuses not blown. do not retry. discard this unit. 1 1 successful. no further program ming is possible . multiple devi ces on one b u s f i gur e 47 sh o w s f o ur ad5170s o n t h e s a m e s e r i al b u s. e a c h has a dif f er en t s l a v e addr es s b e ca us e t h e s t a t es o f t h eir ad0 and ad1 p i n s a r e di f f er en t. this al l o ws e a ch de v i ce o n t h e b u s t o b e wr i t t e n t o , o r r e ad f r o m , i n dep e n d en t l y . th e mas t er de v i ce output bu s l i n e d r ive r s are op e n - d r a i n pu l l - d ow ns i n a f u l l y i 2 c co m p a t i b le in t e r f ace . sda sda ad1 ad0 master scl scl ad5170 sda ad1 ad0 scl ad5170 sda ad1 ad0 scl ad5170 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5170 04104-0-047 f i g u re 47. m u lt ip le a d 51 70s on o n e i 2 c bus
ad5170 rev. a | page 22 of 24 pin conf iguration and fu nction descriptions 10 9 8 7 1 2 3 4 b a ad0 w nc ad1 sda gnd 6 5 scl v dd top view ad5170 04104-0-048 f i gur e 4 8 . p i n c o nfigur a t io n ta ble 10. pi n f u nct i on des c ri pt i o ns p i n m n e m o n i c d e s c r i p t i o n 1 b b t e r m i n a l . 2 a a t e r m i n a l . 3 ad0 programmable address bit 0 for multiple package decoding. 4 g n d d i g i t a l g r o u n d . 5 v dd positive power s u pply. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 ad1 programmable address bit 1 for multiple package decoding. 9 n c n o c o n n e c t . 1 0 w w t e r m i n a l .
ad5170 rev. a | page 23 of 24 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba f i gure 49. 1 0 -l ead m i ni s m al l o u tl ine p a ck ag e [msop ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l r ab (k?) temperature package descri ption package option branding ad5170brm2.5 2.5 C40c to +125c msop-10 rm-10 d0y ad5170brm2.5- rl7 2.5 C40c to +125c msop-10 rm-10 d0y ad5170brm10 10 C40c to +125c msop-10 rm-10 d0z ad5170brm10- rl7 10 C40c to +125c msop-10 rm-10 d0z ad5170brm50 50 C40c to +125c msop-10 rm-10 d0w ad5170brm50- rl7 50 C40c to +125c msop-10 rm-10 d0w ad5170brm100 100 C40c to +125c msop-10 rm-10 d0x ad5170brm100 -rl7 100 C40c to +125c msop-10 rm-10 d0x ad5170eval 1 e v a l u a t i o n bo ar d 1 th e eva l ua t i on boa r d i s sh i pped wi t h t h e 10 k? r a b r e si s t or opt i on ; h o wev e r, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le re si st or va lue opt i on s.
ad5170 rev. a | page 24 of 24 notes purch a se o f li cen s e d i 2 c com p on en t s of an a l o g d e vi ces or on e of i t s sub l i c e n sed a s s o ci a t ed co m p a n i e s con v eys a li cen s e f o r t h e purch a ser un der t h e ph i li ps i 2 c pa t e n t rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 a n al og devic e s , inc . a ll righ ts r e ser v e d . t r a d em arks an d r e gist er e d tr ad emar ks ar e the pr oper t y o f their r e spec tiv e o w ners . d04104C0C 11/04( a )

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